DFT Engineer
*This is a remote position
Description:
- The client is looking for a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.
Responsibilities:
- Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts
- Adhering to the clients ASIC development process.
- Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.
- Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
Required Skills/Knowledge/Experience:
- Bachelors degree in Electrical or Computer Engineering with 8 years of experience, a Masters degree with 6 years of experience
- U.S. Citizenship is required
- Experience in full product life cycle of ASIC Design
- Experience with Cadence and/or Mentor test insertion and ATPG tools
- Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)
- Experience with memory BIST and logic BIST
- Experience generating test patterns and analyzing and debugging test failures
- Experience working with test engineers to implement ATPG vectors on tester hardware
- Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl
- Effective communication and presentation skills and high proficiency in technical problem solving
Preferred Skills/Knowledge/Experience:
- Master’s Degree in Electrical or Computer Engineering
- Expertise of using Cadence Modus DFT tools
- Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
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